PIC16F1825-E/ML【PDF 15/208 页】MCU PIC 14K FLASH 1K RAM 16QFN

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136

ATmega8515(L)

2512K–AVR–01/10

Figure 64. USART Block Diagram

(1)

Note:

1. Refer to Figure 1 on page 2, Table 37 on page 73, and Table 31 on page 69 for

USART pin placement.

The dashed boxes in the block diagram separate the three main parts of the USART

(listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are

shared by all units. The clock generation logic consists of synchronization logic for exter-

nal clock input used by synchronous slave operation, and the baud rate generator. The

XCK (Transfer Clock) pin is only used by Synchronous Transfer mode. The Transmitter

consists of a single write buffer, a serial Shift Register, parity generator and control logic

for handling different serial frame formats. The write buffer allows a continuous transfer

of data without any delay between frames. The Receiver is the most complex part of the

USART module due to its clock and data recovery units. The recovery units are used for

asynchronous data reception. In addition to the recovery units, the Receiver includes a

Parity Checker, control logic, a Shift Register and a two level receive buffer (UDR). The

Receiver supports the same frame formats as the Transmitter, and can detect Frame

Error, Data OverRun and Parity Errors.

PARITY

GENERATOR

UBRR[H:L]

UDR (Transmit)

UCSRA

UCSRB

UCSRC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER

RxD

TxD

CONTROL

UDR (Receive)

CONTROL

XCK

DATA

RECOVERY

CLOCK

RECOVERY

CONTROL

PARITY

CHECKER

DATA

BUS

OSC

SYNC LOGIC

Clock Generator

Transmitter

Receiver

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